The Joint Test Access Group (JTAG) IEEE-1149.1 interface (specification available from www.ieee.org) is widely used for boundary-scan testing and in-system-programming of devices. The JTAG interface is ubiquitous in modern complex ICs to allow for a simple but effective way to test devices at manufacturing time as well as when the parts are assembled in the target system. A block diagram of conventional JTAG circuitry is shown in FIG. 1.
The conventional JTAG data path includes a series of registers placed from the data in (TDI) to the data out (TDO) pin. The clocking, loading and selection of the registers is handled by the test access port (TAP) controller, which is driven by the external pins TRST, TMS and TCLK.
In multi-die or multi-device environments, the components could be connected in series, forming a chain (TDO of component 1 is wired to TDI of component 2, and so on), as illustrated in FIG. 2. In this case, the TRST, TMS and TCLK pins are connected to all of the components. Alternatively, the components can be connected in parallel and share the data pins TDI and TDO, but this scheme requires the use of multiple TMS pins.
Disadvantages of the conventional JTAG technology include that in a multi-die package, there may be multiple copies of JTAG IDs in one packaged device, leading to user and/or test equipment confusion. There may also be longer data latency through the device. Furthermore, the JTAG behavior of N cascaded 1-die devices is the same as that of an N-die device. This fact, coupled with a lack of JTAG ID uniqueness for multi-die devices, can cause problems during test and manufacturing.
It would be desirable to have a solution where devices having multiple die in a boundary scan or JTAG chain have a unique device ID. It would also be desirable for the multi-die device to behave as a single die component from the JTAG interface viewpoint.